List of accepted papers DSD 2012

#	Authors	Title
3	Constantinos Efstathiou, Nikos Moschopoulos, Kostas Tsoumanis and Kiamal Pekmestzi	On the design of configurable modulo 2^n±1 residue generators
4	Jaroslav Sykora, Roman Bartosinski, Lukas Kohout, Martin Danek and Petr Honzik	Reducing Instruction Issue Overheads in Application Specific Vector Processors
13	Evangelos Vassalos, Dimitris Bakalis and Haridimos Vergos	SUT-RNS Residue-to-Binary Converters Design
14	Norbert Druml, Manuel Menghin, Christian Steger, Reinhold Weiss, Andreas Genser, Holger Bock and Josef Haid	Adaptive Field Strength Scaling - A Power Optimization Technique for Contactless Reader / Smart Card Systems
15	Da He and Wolfgang Mueller	A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms
22	René Krenz-Baath, Friedrich Hapke, Rolf Hinze, Andreas Glowatz, Reinhard Meier and Maija Ryynaenen	Robust Evaluation of Weighted Random Logic BIST Structures in Industrial Designs
25	Timo Schönwald, Alexander Viehl, Oliver Bringmann and Wolfgang Rosenstiel	Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures
26	Kolin Paul, Chinmaya Dash and Mansureh Moghaddam	reMORPH -- A Runtime Reconfigurable Architecture
33	Halil Kukner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins and Guido Groeseneken	Impact of duty factor, stress stimuli, and gate drive strength on gate delay degradation with an atomistic trap-based BTI model
35	Sujoy Sinha Roy, Chester Rebeiro and Debdeep Mukhopadhyay	A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms
38	Ioannis Sourdis, Christos Strydis, Christos-Savvas Bouganis, Babak Falsafi, Georgi N. Gaydadjiev, Alirad Malek, Riccardo Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard Rauwerda, Kim Sunesen and Stavros Tzilis	The DeSyRe project: on-Demand System Reliability
43	Syed Mohammad Asad Hassan Jafri, Liang Guang, Ahmed Hemani, Juha Plosila, Kolin Paul and Hannu Tenhunen	Energy-aware Fault-tolerant Network-on-chips for Addressing Multiple Trafﬁc Classes
45	Radhika Jagtap, Sumeet S. Kumar and Rene Van Leuken	A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs
46	Dionisios Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Oliver Pell, Christian Pilato, Mathieu Robart, Marco Santambrogio, Donatella Sciuto, Dirk Stroobandt and Tim Todman	FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconﬁguration
49	Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou and Luciano Lavagno	FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels
52	Gian Mario Bertolotti, Andrea Cristiani, Remo Lombardi and Nikola Serbedzija	The Seat Adaptation System of REFLECT Project: Implementation of a Byocibernetic Loop in an Automotive Environment
54	Juergen Becker, Michael Huebner, Timo Stripf, Steven Derrien, Daniel Menard, Olivier Sentieys, Gerard Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas and Diana Goehringer	From Scilab To High Performance Embedded Multicore Systems – The ALMA Approach
55	João M.P. Cardoso, Tiago Carvalho, José G.F. Coutinho, Pedro Diniz, Zlatko Petrov and Wayne Luk	Controlling Hardware Synthesis with Aspects
59	Bahareh Pourshirazi and Ali Jahanian	RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing Congestion
62	Anna Bernasconi, Valentina Ciriani, Gabriella Trucco and Tiziano Villa	Projected Don't Cares
65	Olivera Jovanovic, Iuliana Bacivarov, Peter Marwedel and Lothar Thiele	MAMOT: Memory-Aware Mapping Optimization Tool for MPSoC
78	Alexandre Chagoya-Garzon, Frédéric Pétrot and Frederic Rousseau	Multi-Device Driver Synthesis Flow for Heterogeneous Hierarchical Systems
79	Carina Schmidt-Knorreck, Daniel Knorreck and Raymond Knopp	IEEE 802.11p Receiver Design for Software Defined Radio Platforms
80	Alberto Bonanno, Alessandro Sanginario, Marco Crepaldi and Danilo Demarchi	An Hardware-In-the-Design Methodology for Wireless Sensor Networks based on Event-Driven Impulse Radio Ultra-Wide Band
81	Prashant Agrawal, Kanishk Sugand, Martin Palkovic, Praveen Raghavan, Liesbet Van der Perre and Francky Catthoor	Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms
83	Chiraz Trabelsi, Samy Meftali and Jean-Luc Dekeyser	Semi-distributed control for FPGA-based reconfigurable systems
86	Meisam Abdollahi, Mohammad Khavari Tavana, Somayyeh Koohi and Shaahin Hessabi	ONC3: All-Optical NoC based on Cube-Connected Cycles with Quasi-DOR Algorithm
88	Raphael Poss, Mike Lankamp, Chris Jesshope, Michiel W. van Tol, Qiang Yang and Jian Fu	: Microgrids of cores Flexible, general-purpose, fine-grained hardware concurrency management(Invited Paper)
93	Dimitris Bekiaris and George Economakos	Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain
94	Sheng Hao Wang, Anup Das, Akash Kumar and Henk Corporaal	Minimizing Power Consumption of Spatial Division based Networks-on-Chip Using Multi-Path and Frequency Reduction
95	Lech Jozwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri and Luigi Raffo	ASAM: Automatic Architecture Synthesis and Application Mapping
104	Omid Assare, Mahmoud Momtazpour and Maziar Goudarzi	Accurate Estimation of Leakage Power Variability in Sub-Micrometer CMOS Circuits
105	Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani and Mehdi Sedighi	OWQS: One-Way Quantum Computation Simulator
106	Felix Miller, Thomas Wild and Andreas Herkersdorf	TSV-Virtualization for Multi-Protocol-Interconnect in 3D-ICs
108	Luciano Lavagno, Mihai Lazarescu, Johan Walters, Bart Kienhuis, Ioannis Papaefstathiou, Andreas Brokalakis and Florian Schaefer	HEAP: a Highly Efficient Adaptive multi-Processor framework
122	Nicolas Celedon, Rodolfo Redlich and Miguel Figueroa	FPGA-Based Neural Network for Nonuniformity Correction on Infrared Focal Plane Arrays
127	David Kramer and Wolfgang Karl	A Scalable Monitoring Infrastructure for Self-Organizing Many-Core Architectures
128	Varadan Savulimedu Veeravalli, Ulrich Schmid, Andreas Steininger and Thomas Polzer	Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip
130	Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Emanuele Cannella, Todor Stefanov, Onur Derin, Leandro Fiorin and Mariagiovanna Sami	System Adaptivity and Fault-tolerance in NoC-based MPSoCs: the MADNESS Project Approach
131	Matthias Ihmig, Michael Feilen and Andreas Herkersdorf	Analytical Design Space Exploration based on statistically Refined Runtime and Logic Estimation for Software Defined Radios
139	Amitabh Das, Baris Ege, Santosh Ghosh and Ingrid Verbauwhede	Differential Scan Attack on AES with X-Tolerant and X-Masked Test Response Compactor
146	Selma Saidi, Oded Maler and Pranav Tendulkar	Optimal 2D Data Partitioning for DMA Transfers on MPSoCs
149	Zouha Cherif and Jean Luc Danger	An Easy-to-Design PUF based on a single oscillator: the Loop PUF
159	Bahman Arasteh, Ali Mansoor and Seyed Ghassem Miremadi	Using Genetic Algorithm to Identify Soft-Error Derating Blocks of an Application Program
162	Erich Wenger, Thomas Baier and Johannes Feichtner	JAAVR: Introducing the Next Generation of Security-enabled RFID Tags
164	Marcin Rogawski and Kris Gaj	A High-Speed Unified Hardware Architecture for the AES and SHA-3 Candidate Gr{\o}stl
165	Jan Schmidt, Petr Fiser and Jiří Balcárek	The Influence of Implementation Technology on Dependability Parameters
170	Jan Pospisil and Martin Novotny	Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable Hardware
175	Bassem Ouni, Cecile Belleudy and Eric Senn	Energy characterization and classification of embedded operating system services
190	Khalid Latif, Amir-Mohammad Rahmani, Tiberiu Seceleanu and Hannu Tenhunen	Designing a High Performance and Reliable Networks-on-Chip using Network Interface Assisted Routing Strategy
195	Christian El Salloum, Martin Elshuber, Oliver Höftberger, Haris Isakovic and Armin Wasicek	The ACROSS MPSoC – A New Generation of Multi-Core Processors designed for Safety-Critical Embedded Systems
197	Kim Gruttner, Philipp Hartmann, Kai Hylla, Sven Rosinger, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Davide Quaglia, Wolfgang Nebel, Chantal Ykman-Couvreur, Francisco Ferrero, Raul Valencia, Fernando Herrera and Eugenio Villar	COMPLEX - COdesign and power Management in PLatform-based design space EXploration
2	Meng Yang	Finite State Machine Synthesis Based on Relay-Based algorithm
6	H. Gregor Molter, Johannes Kohlmann and Sorin A. Huss	Automated Generation of Embedded Systems Software from timed DEVS Model of Computation Specifications
10	Roland Dobai, Marcel Balaz and Maria Fischerova	Automated Generation of Built-in Self-Repair Architectures for Random Logic SoC Cores
12	Abdul Naeem, Axel Jantsch and Zhonghai Lu	Architecture Support and Comparison of Three Memory Consistency Models in NoC based Systems
17	Manel Ammar, Mouna Baklouti and Mohamed Abid	Extending MARTE to support the specification and the generation of data-intensive applications for Massively Parallel SoC
18	Yousra Alkabani	Trojan Immune Circuits Using Duality
20	Jo Vliegen, Karel Wouters, Christian Grahn and Tobias Pulls	Hardware Strengthening a Distributed Logging Scheme
21	Ali Senturk and Mustafa Gok	Pipelined Large Multiplier Designs on FPGAs
28	Eugen Leontie, Gedare Bloom, Bhagirath Narahari and Rahul Simha	No Principal Too Small: Memory Access Control for Fine-Grained Protection Domains
29	Josef Strnadel and Frantisek Slimarik	On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels
32	Peter Raab, Stanislav Racek and Juergen Mottok	Reliability of Task Execution during Safe Software Processing
36	Mohammadreza Najafi, Saeed Safari and Zainalabdein Navabi	Soft Error Analysis on Communication Channels in On-Chip Communication Networks
40	Alvaro Diaz Suarez, Raul Diego and Pablo Sanchez	Virtual Platform for Wireless Sensor Network
44	Nelson Silva, Arnaldo Oliveira and Nuno Carvalho	Evaluation of an FPGA-based Reconfigurable SoC for All-Digital Flexible RF Transmitters
47	Armin Krieg, Johannes Grinschgl, Norbert Druml, Christian Steger, Holger Bock and Josef Haid	PROCOMON - An Automatically Generated Predictive Control-Signal Monitor
48	Gervin Thomas, Karthik Chandrasekar, Benny Akesson, Ben Juurlink and Kees Goossens	A Novel Predictor-based Power-Saving Policy for DRAM Memories
51	Mário Véstias, Horacio Neto and Helena Sarmento	Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs
57	Yasar Asgarieh, Mohammad Khabbazian, Mehdi Modarressi and Hamid Sarbazi-Azad	¬A Game Theoretical Thermal–Aware Run–Time Task Synchronization Method for Multiprocessor Systems–on–Chip
61	Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen	Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm
64	Mário Véstias and Horacio Neto	Efficient Parallel Decimal Multipliers and Squarers using Karatsuba-Ofman's Algorithm
72	Adam Klimowicz and Valery Soloviev	The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of States
85	Mario Donato Marino	On-Package Scalability of RF and Inductive Memory Controllers
98	Fabienne Nouvel and Philippe Tanguy	Flexible OFDM waveform for PLC/RF in-vehicle communications.
101	Markus Ulbricht, Heinrich Theodor Vierhaus and Tobias Koal	Activity Migration in M-of-N-Systems by means of Load-Balancing
102	Paolo Roberto Grassi and Donatella Sciuto	Energy-Aware FPGA-Based Architecture for Wireless Sensor Networks
107	Jan Kastil, Martin Straka, Lukas Miculka and Zdenek Kotasek	Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA
114	Elias Baaklini, Hassan Sbeity and Smail Niar	H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors
116	Apostolos Fournaris and Odysseas Koufopavlou	CRT RSA Hardware Architecture with Fault and Simple Power Attack Countermeasures
118	Francesco Bruschi, Marco Domenico Santambrogio, Paolo Roberto Grassi and Sheetal Bhandari	High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing
119	Christian Gleichner and H.T. Vierhaus	Scan Based Tests Via Standard Interfaces
121	Benaoumeur Senouci, Anne Johan Annema, Mark Bentum and Hans Kerkhoff	Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform based Design
125	Davide Bresolin, Luigi Di Guglielmo, Luca Geretti, Riccardo Muradore, Paolo Fiorini and Tiziano Villa	Open Problems in Verification and Refinement of Autonomous Robotic Systems
129	Fernando Herrera, Héctor Posadas, Eugenio Villar and Daniel Calvo	Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE
132	Cor Meenderinck, Anca Molnos and Kees Goossens	Composable Virtual Memory for an Embedded SoC
133	Pedro Miguens Matutino, Hector Pettenghi, Ricardo Chaves and Leonel Sousa	RNS Arithmetic Units for \textit{Modulo} $\{2^n \pm k\}$
135	Syed Rameez Naqvi, Varadan Savulimedu Veeravalli and Andreas Steininger	Protecting an Asynchronous NoC against Transient Channel Faults
136	Oussama Lazrak, Pierre Leray and Christophe Moy	HDCRAM Proof-of-Concept for Opportunistic Spectrum Access
142	Vincent Berg, Dominique Noguet and Xavier Popon	A Flexible Hardware Platform for Mobile Cognitive Radio applications
145	Jaroslav Borecký, Martin Kohlík and Hana Kubátová	Miscellaneous Types of Partial Duplication Modifications for Availability Improvements
150	Paolo Roberto Grassi, Ivan Beretta, Vincenzo Rana and Donatella Sciuto	Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks
152	Bogdan Spinean and Georgi Gaydadjiev	Implementation Study of FFT on Multi-Lane Vector Processors
156	Emad Samuel Malki Ebeid, Franco Fummi and Davide Quaglia	Generation of VHDL code from UML/MARTE sequence diagrams for verification and synthesis
161	Görker Alp Malazgirt, Ender Culha, Alper Sen, Faik Baskaya and Arda Yurdakul	A Verifiable High Level Data Path Synthesis Framework
163	Catalin Bogdan Ciobanu, Georgi Kuzmanov and Georgi Gaydadjiev	Scalability Study of Polymorphic Register Files
166	Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage and Tarik Graba	A Small and High-performance Coprocessor for Fingerprint Match-On-Card
168	Sandro Bartolini and Paolo Grani	A Simple On-chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs
172	Masoumeh Ebrahimi, Masoud Daneshtalab and Juha Plosila	MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip
174	Paolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy and Luca Benini	OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters
177	Tiago Dias, Luís Rosário, Nuno Roma and Leonel Sousa	High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC
181	Abdulkadir Akin, Elif Erdede, Hossein Afshari, Alexandre Schmid and Yusuf Leblebici	Enhanced Omnidirectional Image Reconstruction Algorithm and its Real-Time Hardware
184	Mehmet Kayaalp, Fahrettin Koc and Oguz Ergin	Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due To Electromigration
188	Satish Kumar Sadasivam, Sangram Alapati, Varun Mallikarjunan and Prathiba Kumar	Test Generation Approach for Post-Silicon Validation of High End Microprocessor
191	Alessandra Majani, Maria Chiara Lorena, Francesco Leporati and Giovanni Danese	A hardware accelerator for real time simulation of complex neuronal models
194	George Provelengios, Paris Kitsos, Nicolas Sklavos and Christos Koulamas	FPGA-based Design Approaches of Keccak Hash Function
196	Fardin Derogarian, João Canas Ferreira and Vítor M. Grade Tavares	Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks
9	Jochem H. Rutgers, Marco J.G. Bekooij and Gerard J.M. Smit	Evaluation of a Connectionless NoC for a Real-Time Distributed Shared Memory Many-Core System
11	Roel Jordans, Rosilde Corvino and Lech Jozwiak	Using Algorithm Parallelism Estimation to Constrain Instruction-Set Synthesis for VLIW Processors
31	Fabio Itturriet, Ronaldo Ferreira, Gustavo Girao, Gabriel Nazar, Alvaro Moreira and Luigi Carro	Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors
39	Farhad Mehdipour, Krishna C. Nunna, Koji Inoue and Kazuaki J. Murakami	A Three-Dimensional Integrated Accelerator
53	Leonel Sousa and Samuel Antao	VLSI Reverse Converter for RNS based on the Moduli Set {2^n+1, 2^n-1, 2^{2n+1}-3, 2^{2n}-2}
56	Mehdi Dehbashi, Görschwin Fey, Kaushik Roy and Anand Raghunathan	On Modeling and Evaluation of Logic Circuits Under Timing Variations
60	Samaneh Talebi, Ali Jahanian and Niloofar Abolghasemi	EJOP: an Extensible Java Processor with Reasonable Performance/Flexibility Trade-off
63	Silvia Franchini, Antonio Gentile, Giorgio Vassallo, Salvatore Vitabile and Filippo Sorbello	A dual-core coprocessor with native 4D Clifford algebra support
69	Shuo Yang, Robert Wille, Daniel Grosse and Rolf Drechsler	Coverage-driven Stimuli Generation
71	Mostafa Moazzen, Akram Reza and Midia Reshadi	CoolMap: A Thermal-Aware Mapping Algorithm For Application Specific Networks-on-Chip
89	Cameron Patterson, Thomas Preston, Francesco Galluppi and Steve Furber	Managing a Massively-Parallel Resource-Constrained Computing Architecture
92	Robert Lorentz and Kris Gaj	Evaluation of the Hardware Performance Space of SHA-3 Candidates Blue Midnight Wish and CubeHash using FPGAs
112	Somayeh Kashi and Morteza Sahebzamani	Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins
113	Alexander Bochem, Kenneth Kent and Rainer Herpers	FPGA based Real-Time Tracking Approach with Validation of Precision and Performance
115	Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang and Takeshi Fujino	Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit
117	Marcel Steine, Marc Geilen and Twan Basten	A Distributed Feedback Control Mechanism for Quality-of-Service Maintenance in Wireless Sensor Networks
120	Marcel Dombrowski, Kenneth B. Kent, Yves Losier, Adam Wilson and Rainer Herpers	Analyzing Bus Load Data Using an FPGA and a Microcontroller
124	Pablo González De Aledo, Javier González-Bayón and Pablo Sanchez	A virtual platform for performance estimation of many-core implementations
140	Ruben Cabral and Helena Sarmento	High Level Modeling and Simulation of a Baseband Processor for the 60 GHz Band
141	Jian Wang, Andreas Karlsson, Joar Sohl and Dake Liu	Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel Memory
151	Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto and Marco Domenico Santambrogio	On the Development of a Runtime Reconfigurable Multicore System-on-Chip
155	Raimund Ubar, Sergei Kostin and Jaan Raik	How to Prove that a Circuit is Fault-Free?
158	Rosilde Corvino, Erkan Diken, Abdoulaye Gamatie and Lech Jozwiak	Transformation-based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study
179	Parinaz Sayyah, Francesco Stefanni, Luciano Lavagno and Davide Quaglia	SystemC model generation for realistic simulation of networked embedded systems
185	Mehmet Kayaalp, Fahrettin Koc and Oguz Ergin	Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-in Comparators